The present invention relates to an electrically erasable programmable read only memory cell (EEPROM) which can be written directly without first erasing the cell. In addition, the present invention relates to a floating gate EEPROM structure which utilizes silicon nitride as the tunneling dielectric, and to methods for direct-writing the structure to high and low threshold states, here termed VT1 and VT0.
The advantages of the above-mentioned direct write scheme over conventional erase/write schemes are that it eliminates the circuitry required for performing the erase operation and shortens the programming time by eliminating the erase operation.
There are available electrically alterable, nonvolatile memories which use a so-called "transparent erase". This refers to the fact that the user does not have to instruct the part to erase a given location prior to writing data into that location. To the user, it looks like direct write but internally the part has to go through an erase operation before writing and thus requires the associated circuitry.
The first generation of floating gate programmable ROMs were poly(polycrystalline silicon) structures which were programmed by driving the drain junction to avalanche breakdown to generate so-called "hot" electrons which had sufficient energy to tunnel through the thick gate oxide between the drain and the isolated floating gate. These devices were termed FAMOS as an acronym for their floating gate, avalanche injection MOS characteristics. FAMOS devices, which are members of the class of devices known as electrically programmable ROMs, are erased by irradiating the device with ultraviolet light.
The second generation programmable ROMs include electrically erasable EEPROM devices. EEPROM technology includes both two-level and three-level structures. In the two-level approach, the second-level polysilicon control gate is capacitively coupled to the underlying gate of a floating gate MOS transistor structure during electrical writing and erasing. As a consequence, the floating gate can be written by applying high voltage to the control gate and ground to the underlying drain. The cell is erased by reversing the polarities.
The three-level stacked EEPROM floating gate cell is potentially perhaps the most efficient floating gate cell in terms of its size and density. Typically, in such a three-level poly EEPROM structure, the first level poly layer includes a reference/ground conductor, the second layer poly includes the floating gate and the third level poly includes a programming/erase electrode. The reference conductor and the floating gate are processed to have upper surface regions containing asperities. These regions generate small currents at locally high electric fields which are sufficient for tunneling charge between the conductors.
Referring now to FIG. 1, there is shown schematically a version of an asperitic three-level nonvolatile memory cell which is disclosed in U.S. Pat. No. 4,274,012. The cell 10 features a diffused bias electrode which is used to effect programming and erasing by capacitive coupling. The relevant elements of the cell include the n+ bias electrode 15 formed in p-type substrate 11, and the overlying, stacked three-layer asperitic sandwich elements comprising program electrode 12, floating gate 13 and store/erase electrode 14. Asperite regions 16 and 17 are formed on the upper surfaces of the program electrode 12 and the floating gate 13 for creating the localized electric fields which permit tunneling through the relatively thick oxide regions 18 and 19. The use of the asperites to enhance tunneling characteristics avoids the necessity of forming thin tunneling oxide layers in large volume commercial production operations.
To write the structure 10, program electrode 12 and transistor gate 20 are set at system ground, V.sub.SS, and a positive high voltage +V.sub.W is applied to the store/erase gate electrode 14. The program voltage is capacitively coupled via the electrically-floating bias electrode 15 to the floating gate 13, thereby causing electrons to tunnel from the low-potential, program plate 12. To erase, V.sub.SS is applied to the bit line 21 and the associated transistor 20 is turned on to connect the V.sub.SS low potential bit line 21 to the bias electrode 15 so that the floating gate 13 is held at V.sub.SS by capacitive coupling. Simultaneously, the positive write voltage, +V.sub.W is applied to the store/erase electrode 14 to tunnel electrons from the low potential floating gate 13 to the store/erase electrode 14.
The floating gate 13 also serves as the gate of a MOS sense transistor. In the above WRITE 1 or VT1 state, with electrons maintaining the floating gate 13 at a low potential, the sense transistor is held off. Conversely, in the WRITE 0 or VT0 state, floating gate 13 is at a relatively high potential for turning on the associated remote sensing transistor.
The primary advantage of the asperitic cell appears to be that the oxides in the charge transfer regions are or can be considerably thicker than the approximately 100 angstrom thickness used by other such cells. Such thick oxides, perhaps 800 angstroms, can enhance process reproducibility and yields. However, this advantage in the use of asperities or textured poly is accompanied by relatively low endurance (that is, the maximum number of write and erase cycles for which the thresholds VT1 and VT0 can be reliably set). The advantage is also accomplished at the cost of using the asperitic structure and of the accompanying additional process and structure complexity which are inherent to the required three-level poly arrangement. Three levels or layers of polysilicon are required because the textured asperite surfaces can be formed only on the upper surface of the poly and because electron tunneling from the asperite is essentially unidirectional, that is, from the asperitic upper poly surface such as 16 and 17 to the overlying poly layer such as 13 and 14. Other disadvantages include the stringent processing controls which are necessary to maintain a uniform, reproducible surface texture for field emission from the asperitic polysilicon and the reliability of the textured polysilicon oxide.
Accordingly, it is an object of the present invention to provide a direct-write nonvolatile memory cell without the structural and operational constraints of the above-described three-layer poly, asperitic cell.
It is another object of the present invention to provide a simplified direct-write EEPROM cell, that is, an EEPROM memory cell which can be written to a high or low threshold state regardless of the previous threshold state and without first erasing the cell.
It is still another object of the present invention to provide a direct-write EEPROM structure which uses silicon nitride as the dielectric in the critical capacitive-coupled conductance paths.
It is still another object of the present invention to provide a direct-write EEPROM cell adapted to use a low programming voltage and on-chip programming voltage generation using a single five volt power supply.
In one aspect, the present invention relates to a nonvolatile electrically alterable memory cell which comprises a substrate control node or electrode, first and second programming or write electrodes, and a floating gate electrode, arranged so that charge transferred between the floating gate and the two write electrodes programs the floating gate to respective VT1 or VT0 levels. Silicon nitride is formed between the two write electrodes and the floating gate to enhance the conduction properties of the cell and provide improved programming characteristics and endurance. In addition, the use of silicon nitride permits the use of a relatively simple two-level polysilicon process and structure.
In another aspect the write electrodes are formed from one polysilicon layer and the floating gate is formed from a second polysilicon layer. In still another aspect, one write electrode and the floating gate are formed from separate layers of polysilicon and the second write electrode is replaced by a substrate diffusion line.